Plutux

Semiconductors

Chips, from the fab floor to the income statement

Foundry capacity, HBM supply, packaging bottlenecks and export rules — traced through to the companies whose quarters they decide.

2026-08-19

Analog Devices ADI calls out AI-linked signal-chain strength—showing analog demand is no longer the “late” trade, it’s the supply bottleneck insight cover
Earnings
ADI7 min read

Analog Devices ADI calls out AI-linked signal-chain strength—showing analog demand is no longer the “late” trade, it’s the supply bottleneck

Analog Devices’ latest guidance commentary reinforces that AI capex is spilling into mature-node analog/mixed-signal—power management, data converters, and upstream signal conditioning—rather than staying confined to GPUs. The investor takeaway: the next constraint may be not compute, but the analog “plumbing” that turns electricity into usable, low-noise data in data-center racks.

FY2025 revenue: $11.02BFY2025 net income: $2.27B
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Etched’s $21B jump signals that inference silicon is moving from “experiment” to “economics”—and it pressures Nvidia’s GPU advantage on both cost and capacity insight cover
Private Company
7 min read

Etched’s $21B jump signals that inference silicon is moving from “experiment” to “economics”—and it pressures Nvidia’s GPU advantage on both cost and capacity

Etched’s Aug. 18 financing valued the company at $21B after a prior $10.3B valuation just weeks earlier—an investor re-rate that coincides with first customer delivery to Jane Street and more than $1B in customer contracts. The market takeaway is not “another chip startup,” but a shift toward dedicated inference hardware that competes with GPUs on two fronts: utilization/cost per token and rack-level capacity to meet urgent decoding demand.

Aug. 18 financing: $700MAug. 18 implied valuation: $21B
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Velaura AI’s $110M Series A reframes the AI power bottleneck as an “inside-the-silicon” battleground insight cover
Private Company
8 min read

Velaura AI’s $110M Series A reframes the AI power bottleneck as an “inside-the-silicon” battleground

Velaura AI raised $110M in a Series A and says its Titan Core silicon design can enable up to 2x lower chip power (up to ~500W savings vs a typical 1000W GPU/XPU) and cut math energy 2–4x. If hyperscalers scale this as a licensing layer, it could compress “compute-per-rack” economics and shift budgeting from just grid and cooling toward silicon efficiency—pressuring incumbent custom-silicon economics while benefiting thermal/power infrastructure winners.

Velaura’s power lever: Up to 2x lower chip powerIllustrative savings: Up to ~500W saved
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2026-08-18

2026-08-17

The 48V rack bus is the new price bottleneck in AI data centers—SiC/GaN power silicon may capture the “dollars-per-watt” upside that electrical OEMs can’t insight cover
Supply Chain
9 min read

The 48V rack bus is the new price bottleneck in AI data centers—SiC/GaN power silicon may capture the “dollars-per-watt” upside that electrical OEMs can’t

As AI racks scale toward hundreds of kilowatts, the in-rack power-delivery chain (PSU → 48V bus → VRMs → SiC/GaN switching) is getting harder to build, cool, and qualify as one stack. Primary disclosures show that the Vera Rubin NVL72 rack design already concentrates power demand into multiple 110kW shelves, while grid-side electrical backlogs (Eaton) and 800V HVDC guidance (onsemi) point to a multi-year build-out. Investors should expect silicon vendors supplying SiC/GaN efficiency and density to monetize the “per-watt” upgrade cycle faster than the grid/electrical OEM layer.

Vera Rubin NVL72 rack power shelves: 4 × 110 kWEaton Electrical sector backlog growth: +43%
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Fabrinet will try to prove the 800G→1.6T ramp is shipping, not just selling design wins insight cover
Earnings
FN7 min read

Fabrinet will try to prove the 800G→1.6T ramp is shipping, not just selling design wins

Fabrinet’s Q4 FY2026 report is the first high-signal check from the ODM layer of AI optical supply chains: it turns optical module “qualification” into product shipments and margin. Investors should focus on whether optical communications revenue mix and gross margin expand together, and whether working-capital swings look consistent with a real production ramp into larger-capacity transceivers.

FY2026 scope reminder: FY2026 ended Jun 26, 2026Q4 FY2026 is the “volume vote”: Q4 FY2026 report
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Keysight’s Q3 print is a live test for whether 1.6T optical designs are actually clearing validation—before the “shipping” headline hits revenue insight cover
Earnings
KEYS7 min read

Keysight’s Q3 print is a live test for whether 1.6T optical designs are actually clearing validation—before the “shipping” headline hits revenue

Keysight’s communications-solutions orders are one of the earliest demand signals in the AI networking supply chain, because hyperscalers and optical-module makers must validate stressed electrical/optical designs on Keysight test platforms before 1.6T systems ship. With Keysight reporting this week, the key question isn’t “is AI spend real?”—it’s whether design-validation orders are accelerating fast enough to confirm the optical rally hasn’t priced only aspirations.

Orders: Over $2.05BCommunications Solutions Group revenue: $1.231B
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Nvidia’s “$1T through 2027” target resets the AI capex scare into a system-scale test insight cover
Earnings
7 min read

Nvidia’s “$1T through 2027” target resets the AI capex scare into a system-scale test

Nvidia says it now sees at least $1T in AI-chip demand through 2027—framed as a doubling from an earlier ~$500B view. Investors should treat the Aug. 26 quarter as the feasibility checkpoint: can memory, advanced packaging, power, and networking expand fast enough to convert that visibility into shipments without forcing an avoidable margin or cash crunch?

Updated demand visibility: $1T+ through 2027Implied doubling vs prior view: ~2x
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SanDisk’s “$94B backlog + 80% gross-margin” promise turns NAND into a contracting business—but the key test is whether the pricing floor survives insight cover
Earnings
7 min read

SanDisk’s “$94B backlog + 80% gross-margin” promise turns NAND into a contracting business—but the key test is whether the pricing floor survives

Western Digital’s SanDisk business claims multi-year visibility through a very large contracted backlog and an 80% gross-margin target through 2030. For investors, the trade is no longer “is NAND still commodity,” but “do hyperscalers sustain committed demand without forcing renegotiations, and does the cost stack keep up with 80% economics?”

Western Digital revenue (TTM): $12.92BWestern Digital gross profit (TTM): $6.31B
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ATE is the real AI bottleneck: Advantest and Teradyne own the “last meter” on shipping HBM-heavy silicon insight cover
Supply Chain
TER8 min read

ATE is the real AI bottleneck: Advantest and Teradyne own the “last meter” on shipping HBM-heavy silicon

As HBM stacks and chiplet complexity multiply test vectors, test floor throughput and “known-good” screening—not EUV—can become the binding constraint on how fast AI chips convert into shippable units. Teradyne and Advantest are positioned as critical enablers because they sell the platforms (and test pattern memory/architecture) that make high-throughput memory and compute testing feasible.

Teradyne revenue: $2.82BTeradyne gross profit: $1.65B
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2026-08-16

2026-08-15

2026-08-14

2026-08-13

2026-08-12

What to expect

Evidence-first notes with a visible point of view.

This section collects sharp takes on earnings, shareholder meetings, and market structure. Each new piece should make the thesis, the facts, and the implications obvious within the first few screens.

Expect direct analysis, not generic commentary.

Expect the data to be explicit and the argument to be easy to follow.

Plutux is not an investment adviser. Market data and AI-generated analysis are for information and education only, not investment advice. Disclaimer

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