Technology
The largest buyers of AI compute are also, increasingly, chip designers. A custom accelerator gives up flexibility and takes on design risk in exchange for a lower cost per unit of work on a workload the buyer already knows in detail.
In one sentence
A custom AI ASIC is an accelerator designed by or for a single operator, targeting the specific models and serving patterns that operator runs, rather than sold as a general-purpose part.
The case for building one is arithmetic. If a company will spend billions of dollars a year running one narrow class of workload, a design that removes everything that workload does not use — and adds exactly the memory and interconnect it does — can beat a merchant part on cost per token by enough to pay for a chip team many times over.
The case against is that the chip takes two to three years from specification to deployment, and the workload it was specified for may not be the workload that matters when it lands. This is why custom parts have historically targeted inference and stable, high-volume internal services before they targeted frontier training.
Rarely the operator alone. The architecture and the parts that encode the workload are in-house; the physical implementation, the high-speed interfaces, the packaging and the relationship with the foundry usually come from a design-services partner. That is a real business line for the large merchant silicon vendors, and it means an in-house chip still routes through the same foundry and packaging queues.
Out go graphics blocks, most of the general-purpose programmability, and support for numeric formats the operator does not use. In go arithmetic units matched to the operator's model shapes, on-chip memory sized to its layers, and interconnect matched to how its clusters are wired. The result is efficient on that workload and awkward on anything else.
A second source changes a negotiation. Even a custom part that never displaces the majority of a fleet changes what the merchant vendor can charge for the rest of it, which is why the programme is often worth running before the chip is competitive on its own terms.
3 of these are marked as a chokepoint: a handful of qualified suppliers, a multi-year lead time, or a single geography.
SerDes, memory controllers, packaging expertise and physical implementation are bought in. Very few organisations carry all of it internally.
Semiconductor IPA custom part competes for exactly the same wafers and the same packaging slots as the merchant parts it is meant to displace.
Foundry vs IDMCustom silicon with no compiler is unusable. The software effort is comparable to the hardware effort and is the usual reason a programme slips.
Programming modelsCustom parts bid for the same constrained memory stacks as merchant accelerators, from the same three suppliers.
High-bandwidth memoryA custom part with stacked memory needs the same silicon interposer and the same assembly line as a merchant accelerator, and it joins the same queue for them.
Interposers and 2.5DOperator parts are usually assembled from several dies so that a compute die can be re-spun without redoing the interfaces. Without a working die-to-die link the design collapses back to one reticle-limited chip.
ChipletsTiming, power and physical verification are done in the same licensed tool flow the merchant vendors use. A tape-out that fails sign-off costs a mask set and a quarter.
EDA toolsOther pages in this map that name Custom AI ASICs as something they cannot do without.
What each company supplies at this step, and — where a public figure exists — its share of this specific market — with what that share measures, the period it covers and who published it. Some rows also show the company’s own reported revenue for the segment covering this step, which is a different thing: it says how much this business matters to that company, not how much of the market it holds. Not a ranking and not a recommendation.
Co-designs and supplies custom accelerators and the high-speed interfaces around them for large operators.
Provides custom silicon design services, SerDes and interconnect IP for operator-specific accelerators.
Designs and deploys its own accelerator line for internal training and serving.
Designs in-house training and inference accelerators offered through its cloud.
Designs the Maia accelerator to reduce what it buys for its own fleet.
Designs the MTIA accelerators for its ranking and recommendation workloads.
Supplies the physical design and production services behind several of these chips.
Co-designs operator accelerators and supplies the physical implementation behind several of them.
Provides the design-services path from an operator's architecture to a manufacturable part at the leading edge.
Is co-designing an accelerator for its own serving fleet with a merchant silicon partner.
Designs both its training silicon and the inference part in the car, the only vehicle maker doing either at scale.
Designs the Hanguang inference accelerator and the server processor beside it through its own silicon unit.
Designs the inference accelerators it runs internally, and funds a merchant accelerator designer alongside them.
Designs the Kunlun line and deploys it in its own cloud — the longest-running operator silicon programme in China.
Offers the turnkey path — foundry, packaging and memory from one company — to operators who would rather not assemble three suppliers.
Takes an operator's architecture to a manufacturable part, the Japanese counterpart to the Taiwanese design-service houses.
Co-designs its own inference silicon with merchant partners to cut what it buys for recommendation and model serving.
Whether custom parts move from inference into frontier training at scale, or stay on stable high-volume workloads.
Whether design-services capacity — not foundry capacity — becomes the limit on how many custom programmes can run at once.
How much of a fleet has to be custom before the pricing effect on merchant parts is the main return on the programme.
Each page explains one technology in plain language, states what it depends on, and names companies by what they supply at that step. Company roles are described qualitatively and deliberately carry no market shares, revenue figures or rankings — those change faster than an explainer can, and a stale number is worse than none. Ticker links point at company pages on this site and are provided for reference only.
Nothing here is investment advice, a recommendation, or a forecast. A company named on a page about a technology is not thereby a good investment, and the chokepoints described are structural facts about supply chains rather than predictions about prices. Technology moves; where a page describes something as unresolved or in development, that was true when it was written.
Plutux is not an investment adviser. Market data and AI-generated analysis are for information and education only, not investment advice. Disclaimer