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Eliyan’s $145M/ $1B chiplet-memory bet turns NVLink into a testable “standard,” not a monopoly insight cover
Industry NewsNVDA · TSM · AMKR8 min read

Eliyan’s $145M/ $1B chiplet-memory bet turns NVLink into a testable “standard,” not a monopoly

Eliyan’s $145M Series C at a $1B valuation funds an electro-optical die-to-die/die-to-memory interconnect platform aimed at removing AI chip data bottlenecks. Because Eliyan positions NuLink as standards-compatible (UCIe/BoW) and targets bandwidth efficiency for chiplet-to-memory traffic, it pressures the idea that Nvidia’s NVLink is the only path to coherent “big memory” scale.

Published Jul 30, 2026Updated Jul 30, 2026

Eliyan round size

$145M

Series C announced July 29, 2026 (Reuters + Eliyan press page)

Eliyan post-money valuation claim

$1B

Valuation stated with the round (Reuters + Eliyan press page)

NuLink interoperability claim

UCIe/BoW

Protocol-agnostic support stated on Eliyan technology page

D2M bandwidth efficiency claim

“doubling” beachfront bandwidth

Eliyan technology page language on memory traffic bandwidth

The verified event

Eliyan closed a $145M Series C at a $1B valuation to tackle AI “chip data bottlenecks,” not just networking

Eliyan Eliyan (private) announced on July 29, 2026 that it raised a $145M Series C at a $1B valuation to ease bottlenecks in moving data between AI chips in data centers. In parallel, Eliyan’s CEO described the mechanism bluntly: most AI GPUs are limited by how fast they can receive data to process—leading to materially underutilized compute capacity.

  • raised $145M at a $1B valuation to scale its AI die-to-die/die-to-memory interconnect platform
  • targets bottlenecks in transferring data between AI chips (a compute-idle problem, not a pure software scheduling problem)
  • plans initial chiplet shipments this year and forecasts hundreds of millions in sales by end-2027 (per Reuters)
What the funding announcement actually establishes (facts only)
FactStated amount / metricWhat it implies
Round size and valuation$145M; $1B valuationInvestor confidence in interconnect as a standalone category
Use of proceeds (high level)Expand next-generation interconnect development/products; scale manufacturingExecution risk remains, but the company is committing to productization
CEO framing of the bottleneckMost AI chips process data faster than they can send/receive it; idle waitingThe “memory wall” thesis is treated as a system-level bandwidth constraint

The technology claim and the “standard” angle

NuLink’s positioning matters: standards-compatible PHYs aim to make die-to-die “memory sharing” measurable beyond Nvidia’s stack

Eliyan Eliyan describes NuLink as a die-to-die PHY optimized for high-speed serial connections, with extensions into die-to-memory (D2M) and rack-scale optical fabrics. Crucially for investors tracking Nvidia’s ecosystem lock-in thesis, Eliyan explicitly states NuLink is protocol-agnostic and fully supports industry standards including UCIe and BoW, rather than only a proprietary NVIDIA-style interconnect plane.

Eliyan’s “pressure test” on NVLink is conceptual: it markets NuLink as standards-compatible (UCIe/BoW), so performance claims can be evaluated with third-party die-to-die implementations rather than remaining siloed inside one vendor’s interconnect + coherency design.
  • claims NuLink is optimized for high-speed serial die-to-die connections (PHY layer foundation for D2D fabrics)
  • claims simultaneous bidirectional signaling (SBD) to increase effective bandwidth per interface for D2D designs
  • states NuLink provides die-to-memory (D2M) solutions and discusses “doubling” beachfront bandwidth for memory traffic

Causal chain: why this hits “HBM as the wall,” not “software as the wall”

If GPUs wait on data, faster die-to-die and die-to-memory links can reduce “idle compute” before they ever increase model FLOPs

Reuters reports Eliyan’s CEO arguing that data movement is the gating factor: GPUs may process data faster than they can receive it, leaving compute waiting. That reframes the “AI memory wall” as a transport-and-protocol problem: if the interconnect between compute tiles and memory tiles cannot sustain the required read/write patterns (or the coherency/translation overhead is too costly), adding more HBM per GPU won’t fully eliminate the idle time.

Nvidia’s recent scale suggests why interconnect efficiency becomes financially material (revenue and income growth trend)

Illustrative context from listed financials; not a direct interconnect measurement.

Unit: USD

FY2024 revenue

60,922,000,000

FY2025 revenue

130,497,000,000

FY2026 revenue (FY 2026)

215,938,000,000

TTM (latest)

253,491,000,000

  • frames the bottleneck as GPU idle time awaiting incoming data (per Reuters CEO commentary, $-value is implicit in higher cluster utilization)
  • implies that smarter PHY/interconnect changes utilization first, which can outrun incremental changes to model compute density
  • makes “memory wall” partly a packaging-and-protocol problem, because die-to-memory bandwidth efficiency is constrained by physical link + signaling

Supply-chain map (upstream and downstream named)

This is a full-stack interconnect play: upstream optics/photons, midstream packaging/back-end, and downstream GPU-server deployments

Eliyan’s announcement and technology page describe electro-optical interconnect, chiplet connectivity, and advanced package-level integration. That touches multiple layers in the AI server value chain: (1) board and optical/photonic transport components, (2) foundry and packaging capacity that can actually assemble die-to-die links at the required bump pitches and power budgets, and (3) downstream hyperscaler and OEM server designs that must validate coherency and end-to-end bandwidth.

What gets repriced if die-to-die standards work (mechanism-first view)
Supply-chain layerWhere the value shows up if Eliyan winsTypical listed proxy
Advanced packaging/back-endHigher adoption of die-to-die/die-to-memory PHY-equipped chiplets and multi-die stacksAmkor [AMKR]
Foundry capacity / advanced processesMore demand for chiplets designed to fit standard die-to-die PHYs and packaging constraintsTSMC [TSM]
Optics/photonic transport componentsGreater use of electro-optical interconnect paths (especially for longer reach inside racks)Lumentum [LITE]
System integration / networking planesPotentially more multi-vendor fabrics and less “single-vendor interconnect exclusivity” per rackBroadcom [AVGO]

Investor relevance: what it means for Nvidia’s NVLink thesis (without over-claiming)

NVLink may still be best-in-class—but Eliyan changes the debate from “monopoly” to “benchmarkable interoperability”

Nvidia’s NVLink story has often been framed as a moat because coherent die-to-die fabrics are tightly integrated into platform design choices. Eliyan Eliyan doesn’t disprove that outright. Instead, it attacks the monopoly assumption by positioning a third-party interconnect technology that claims standards support (UCIe/BoW) and targets both die-to-die and die-to-memory bandwidth efficiency—making it possible for system builders to evaluate alternative architectures on common interfaces and packaging regimes.

The practical read-through is: interconnect becomes a “replaceable layer” you can validate on benchmarks, which tends to compress any single-vendor implied pricing power over time—if qualification and reliability timelines line up.

Eliyan round size

$145M

Series C announced July 29, 2026 (Reuters + Eliyan press page)

Eliyan post-money valuation claim

$1B

Valuation stated with the round (Reuters + Eliyan press page)

NuLink interoperability claim

UCIe/BoW

Protocol-agnostic support stated on Eliyan technology page

D2M bandwidth efficiency claim

“doubling” beachfront bandwidth

Eliyan technology page language on memory traffic bandwidth

Horizons: what moves first vs. what takes 1–3 years

Short term: qualification and partner signals. Long term: packaging adoption and measurable multi-vendor interoperability in production AI clusters

  • moves first through qualification cycles: Reuters says initial chiplet shipments are expected this year, so customer evaluation and reliability validation should be the near-term “tell.”
  • moves next through packaging/back-end capacity planning: if chiplet interconnect adoption broadens, advanced packaging constraints become the binding bottleneck, not just memory capacity.
  • ripples into system-level architecture over 1–3 years: standards-compatible D2D/D2M PHYs force vendors to compete on end-to-end performance and power under common interface assumptions.

Key risk: even if the PHY layer claims are strong, interconnect usefulness depends on platform coherency behavior, memory protocol integration, and total system power/thermals. Eliyan’s funding buys time; the market repricing only follows if those integration details work in shipped systems and show clear utilization lift.

Second-order winners/losers grounded in listed financial scale

The “repricing” target set: packaging intensity, optical transport demand, and networking ASIC/Fabric optionality

To avoid turning this into pure narrative, we anchor the investable takeaway to listed-company fundamentals that relate to the interconnect supply chain. Nvidia’s revenue scale has surged to a TTM level of $253.49B, which increases the economic value of cluster utilization improvements. That makes any validated alternative to proprietary interconnect planes potentially important enough to matter to multiple hardware layers—especially those that bottleneck physical assembly and optical reach.

Listed stock linkages (evidence-backed supply-chain exposure to standards-compatible die-to-die/die-to-memory interconnect adoption)

NNVIDIA CorporationNVDA--
--Vol --
-
Bearish
  • faces benchmark pressure on interconnect pricing power if standards-compatible D2D/D2M qualify alongside NVLink, compressing moat expectations over 12–36 months
  • risks incremental cluster utilization gains becoming “multi-vendor” if Eliyan’s approach reduces idle time independently of NVLink integration in production racks
TTaiwan Semiconductor Manufacturing Company LimitedTSM--
--Vol --
-
Bullish
  • stands to gain from more chiplet-integrated process demand if UCIe/BoW-compatible die-to-die designs expand shipped unit volumes over 1–3 years
  • benefits from higher wafer starts for interconnect-enabled accelerators as packaging/fabric qualification cycles pull more compute tiles into mass production
AAmkor Technology IncAMKR--
--Vol --
-
Bullish
  • could see higher advanced packaging content per accelerator if D2D/D2M PHY-equipped chiplets drive more multi-die stack and test flow complexity in the near-to-mid term
  • captures incremental margin upside if qualification reduces rework by scaling standardized die-to-die assembly and verification processes
ABroadcom IncAVGO--
--Vol --
-
Mixed
  • may gain optionality from more heterogeneous fabric architectures if server interconnect layers become multi-vendor rather than single-vendor dependent
  • faces competitive pressure on integrated fabric/networking attach if alternatives reduce the need for one vendor’s end-to-end interconnect coupling
LLumentum Holdings Inc.LITE--
--Vol --
-
Bullish
  • could benefit from increased electro-optical interconnect deployment if longer-reach rack fabrics scale using optics-focused interconnect paths over 1–3 years
  • stands to see demand lift through system-level bandwidth upgrades as the bottleneck shifts from compute to transport and reliability at scale

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