DRAM manufacturing: the wafer capacity every memory tier competes for
High-bandwidth memory, the DIMMs in an AI server and the memory in a phone all come off the same kind of line at the same three companies. That shared origin is why AI demand moves the price of memory in unrelated products, and why the choice of what to build is a capital allocation decision rather than a technical one.
In one sentence
DRAM manufacturing is the fabrication of dynamic random-access memory dies on silicon wafers, a capital-intensive process operated at scale by three companies and shared across every product category that uses DRAM.
A DRAM cell is a transistor and a capacitor, and the difficulty is that the capacitor has to hold enough charge to be readable while occupying an ever-smaller footprint. The answer has been to build it vertically — deep, narrow trenches with very high aspect ratios — which is why memory drives demand for the hardest etch and deposition processes in the industry.
The industry is three companies with fungible capacity. A wafer started as stacked memory is a wafer not started as a commodity module, and stacked memory consumes far more silicon area per gigabyte because of the logic base die and the yield loss in stacking. Allocating capacity toward it therefore tightens everything else, which is the mechanism behind memory price cycles that appear to have nothing to do with their apparent cause.
How it works
Why the cycle is so violent
Three suppliers, a nearly interchangeable product, and capacity that arrives in large increments after a two-year build. When demand exceeds supply, price rises steeply because buyers have no alternative; when capacity lands into a surplus, price collapses because there is no product differentiation to defend. Memory is the most cyclical part of the semiconductor industry for structural reasons.
Scaling has become vertical
Shrinking the cell in two dimensions has slowed, so capacitor structures have gone deeper and process complexity has risen faster than density. That has made memory a major consumer of high-aspect-ratio etch, and it is why the equipment intensity of a DRAM line has climbed even where the node label has barely moved.
Stacked memory eats disproportionate capacity
A stack of dies plus a logic base die, joined with through-silicon vias and yielded as a unit, consumes several times the wafer area per usable gigabyte that a conventional part does. That is why a modest share of bit demand can absorb a large share of wafer capacity, and why the two markets tighten together.
What this depends on
4 of these are marked as a chokepoint: a handful of qualified suppliers, a multi-year lead time, or a single geography.
Supply chainChokepoint
High-aspect-ratio etch and deposition
Vertical capacitor structures are the hardest etch problem in volume manufacturing, and memory is its largest customer.
Most DRAM layers are still printed on immersion tools, several passes each. Scanner deliveries, not cleanroom space, set how quickly a new memory fab reaches volume.
The leading nodes have moved their tightest layers to EUV to remove multi-patterning steps. A maker without EUV access pays for it in cycle time and wafer cost on every die.
Each patterning pass consumes qualified resist and the developers and strippers around it, from a short list of mostly Japanese suppliers. A qualification change is a months-long exercise per layer.
What each company supplies at this step, and — where a public figure exists — its share of this specific market — with what that share measures, the period it covers and who published it. Some rows also show the company’s own reported revenue for the segment covering this step, which is a different thing: it says how much this business matters to that company, not how much of the market it holds. Not a ranking and not a recommendation.
Supplies the silicon wafers underneath all of it; a shortage here caps every manufacturer at once.
What would change the picture
Whether stacked memory keeps absorbing a rising share of wafer capacity.
Whether the three-supplier structure holds or a credible fourth entrant emerges.
Whether vertical scaling continues to raise equipment intensity per wafer.
Questions people ask about this
Why does AI demand raise the price of ordinary memory?
Because it is the same capacity. A wafer allocated to stacked memory is a wafer not allocated to standard modules, and stacked parts consume several times the area per gigabyte. A modest share of demand can therefore absorb a large share of supply, tightening every other memory product.
Why only three suppliers?
Because the product is nearly interchangeable and the capital intensity is extreme, so the industry consolidated to the point where scale is the only durable advantage. Entering now would mean matching decades of process learning while competing on price against fully depreciated capacity.
Each page explains one technology in plain language, states what it depends on, and names companies by what they supply at that step. Company roles are described qualitatively and deliberately carry no market shares, revenue figures or rankings — those change faster than an explainer can, and a stale number is worse than none. Ticker links point at company pages on this site and are provided for reference only.
Nothing here is investment advice, a recommendation, or a forecast. A company named on a page about a technology is not thereby a good investment, and the chokepoints described are structural facts about supply chains rather than predictions about prices. Technology moves; where a page describes something as unresolved or in development, that was true when it was written.