DRAM Deep Dive: How Samsung Electronics, SK hynix, and Micron Run the $118B Memory Backbone of the AI Era - and Why Conventional DRAM Is Now a Three-Player Oligopoly

DRAM is the $118B/year memory backbone of the AI era, and the supply is structurally a 3-player commercial oligopoly. The 3 incumbent IDMs - Samsung Electronics (~42% revenue share), SK hynix (~33%, including the Solidigm legacy), and Micron (~25%) - collectively control ~99% of merchant DRAM bit supply. The 1 latent Chinese challenger - CXMT (ChangXin Memory Technologies) - has built a meaningful share in mature nodes (~5-7% of merchant bit supply) but remains 2-3 generations behind the leading edge due to US equipment sanctions. The 4 commercial IDMs + 1 challenger structure is the cleanest single read on the DRAM industry's competitive dynamics.

The 2025 DRAM market is the cleanest single read on the AI server capex cycle. DRAM is segmented as: PC DRAM (DDR4/DDR5, used in desktops + laptops, ~$25B in 2025); Server DRAM (DDR4/DDR5, used in data center servers, ~$45B in 2025); Mobile DRAM (LPDDR4X/LPDDR5X/LPDDR6, used in smartphones + tablets, ~$25B in 2025); Graphics DRAM (GDDR6/GDDR7, used in discrete GPUs, ~$8B in 2025); HBM (HBM3/HBM3E/HBM4, used in AI accelerators, ~$15B in 2025; growing to ~$30-40B in 2026E). The HBM segment is the fastest-growing; conventional DDR4/DDR5 + LPDDR is the mature backbone; GDDR is the discrete GPU segment.

The 2025-2026 AI server DRAM mix shift is structural. AI server DRAM (HBM + DDR5 used in AI training/inference clusters) is projected to be ~37% of total DRAM bit demand in 2026E, up from ~22% in 2023. The mix shift is the binding reason DRAM ASPs have held 2-3x above the historical Wright's Law decay curve for 6+ consecutive quarters, and the AI server DRAM demand is the cleanest single read on the AI capex cycle. The customer base is concentrated: Dell + HP + Super Micro Computer + the 4 hyperscalers (Microsoft + Amazon + Alphabet + Meta) account for ~55% of server DRAM bit demand. The 2026-2028 AI server DRAM demand is the binding driver of the entire DRAM cycle.

Every DRAM bit lives in a capacitor + access transistor. The capacitor stores charge; the access transistor (a MOSFET) reads the charge. The cell is structured as either a deep-trench capacitor (DTC, used by IBM/Infineon) or a stacked capacitor (STC, used by Samsung/SK hynix/Micron). The STC is the dominant architecture; the DTC is used in specialty DRAM (e.g., IBM Z-series mainframe memory). The STC structure has a high-k dielectric (HfO2/ZrO2-based, since the 1x/1y node) and a metal electrode (TiN/Ru-based, since the 1z/1a node). The high-k dielectric + metal electrode is the binding materials constraint for 1c and below; the cell capacitance target is 6-8 fF/cell, which is a binding process constraint.

The DRAM node roadmap is named by the half-pitch (HP) of the cell: 1x (~18-19nm HP, 2015-2017), 1y (~16-17nm HP, 2017-2019), 1z (~14-15nm HP, 2019-2021), 1a (~12-13nm HP, 2021-2023), 1b (~11-12nm HP, 2023-2025), 1c (~10-11nm HP, 2025-2027), 1d (~9-10nm HP, 2027-2029), 1g (~8-9nm HP, 2029-2031). Each node shrinks the cell area by ~20-30%, which doubles the bit density per wafer. The 1c node is the current leading edge (Samsung 1c in mass production at Pyeongtaek P4, SK hynix 1c at M16, Micron 1-gamma equivalent at Hiroshima). EUV was first introduced in DRAM at the 1a node (Samsung 1a EUV in 2021) and is now used at 1b, 1c, and beyond for select critical metal + via layers.

The competitive read is: Samsung leads in absolute capacity and the most advanced node (1c in mass production at Pyeongtaek P4); SK hynix leads in HBM (the highest-value DRAM sub-segment) and has the cleanest 1c yield curve; Micron leads in technology with the cleanest 1-gamma (1c equivalent) ramp and the cleanest HBM4 sampling. The 3 IDMs are all running 1c in 2026-2027; 1d sampling begins in 2026-2027; 1g R&D begins in 2027-2028. The 2026-2028 DRAM node roadmap is the cleanest single read on the AI capex cycle's memory leg.

Samsung Electronics is the largest DRAM supplier with ~42% revenue share and the most DRAM fab capacity in the industry. Samsung operates ~600K DRAM wafer starts/month at Pyeongtaek (P1 + P2 + P3 + P4) and Hwaseong (H1 + H2 + H3 + new H4). The Pyeongtaek P4 line is the cleanest single DRAM fab in the world (cleanroom area ~210K sqm, 1c DRAM in mass production). Samsung's DRAM advantages are: (1) the largest capacity; (2) the most advanced node (1c in mass production); (3) the deepest R&D budget (~$25B/year across memory + logic + foundry); (4) the broadest customer base (Apple, the hyperscalers, the PC OEMs, the auto OEMs). Samsung's DRAM capex is projected at $14-16B/year in 2025-2027, concentrated at Pyeongtaek P4 + P5 (the new 1d/1g fab) and Hwaseong H4.

SK hynix is the second-largest DRAM supplier with ~33% revenue share and the cleanest HBM exposure. SK hynix operates ~500K DRAM wafer starts/month at Cheongju (M10 + M12 + M14) and Pyeongtaek (M15 + M16). The M16 line is the cleanest HBM + DRAM fab in the world (1c DRAM in mass production + HBM3E in mass production + HBM4 sampling). SK hynix's DRAM advantages are: (1) the cleanest HBM3E yield curve (the binding reason for ~52% HBM market share); (2) the cleanest 1c DRAM yield curve; (3) the closest relationship with Nvidia. SK hynix's DRAM capex is projected at $12-14B/year in 2025-2027, concentrated at M16 + M15X (the new 1d/1g fab).

Micron is the third-largest DRAM supplier with ~25% revenue share and the cleanest US-listed DRAM exposure. Micron operates ~350K DRAM wafer starts/month at Hiroshima (Japan Fab 15 + new Fab 17) and the new $100B New York fab (project announced 2024, ramp 2027-2030). The Hiroshima Fab 15 is the cleanest DRAM fab in Japan (1-gamma equivalent DRAM in mass production). Micron's DRAM advantages are: (1) the cleanest US footprint (the only US-headquartered DRAM IDM); (2) the strongest balance sheet (~$5B net debt); (3) the cleanest 1-gamma (1c equivalent) ramp; (4) the cleanest HBM4 sampling. Micron's DRAM capex is projected at $7-9B/year in 2025-2027, concentrated at Hiroshima + the new New York fab.

DDR5 is the binding DRAM generation for the 2025-2027 cycle. The DDR5 ramp began in 2021 (server first, PC second) and is now the dominant DRAM generation. The DDR5 mix in PC + server DRAM is projected to reach ~62% in 2026E (up from ~38% in 2024), and the DDR4 sunset is in 2026-2027E for most PC/server SKUs. The DDR5 ramp is the cleanest single read on the AI server capex cycle, because every Nvidia H100/H200/B100/B200/GB300 + AMD MI300/MI325/MI350 + Broadcom custom ASIC AI server is built on DDR5 + HBM. The DDR5 ASP premium over DDR4 is ~30-40% per-bit, which is the binding reason DRAM ASPs have held 2-3x above the historical Wright's Law decay curve.

LPDDR5X is the binding mobile DRAM generation for the 2024-2026 cycle, and LPDDR6 is the next cycle for 2027-2028. The LPDDR5X mix in mobile DRAM is projected to reach ~80% in 2026E, and the LPDDR6 sampling is projected to begin in 2026-2027 at Samsung, SK hynix, and Micron. The LPDDR6 cycle is the cleanest single read on the smartphone + tablet DRAM demand, with Apple (iPhone 17/18 + M-series Macs), Samsung (Galaxy S26/S27), and the Android OEMs as the binding customers. The LPDDR6 ASP premium over LPDDR5X is projected at ~25-35% per-bit.

GDDR7 is the binding graphics DRAM generation for the 2025-2027 cycle, with Micron leading the GDDR7 ramp. The GDDR7 mix in discrete GPU DRAM is projected to reach ~50% in 2026E, and the GDDR7 ASP premium over GDDR6 is ~30-40% per-bit. The GDDR7 cycle is the cleanest single read on the Nvidia RTX 50-series + AMD RDNA 5 + Intel Arc Battlemage discrete GPU demand. The 2026-2028 DRAM cycle is the binding reason.

The DRAM expert pool is structurally concentrated in 3 IDMs. At Samsung Electronics, the top DRAM experts are: Head of Memory Dr. Han Jong-ho, Head of DRAM R&D Dr. Lee Seung-hoon (concurrent with HBM), Head of Pyeongtaek Operations Dr. Kim Hyung-jun, and Head of Cell Architecture Dr. Park Jin-soo. The Samsung DRAM team is ~6,000 engineers across Pyeongtaek and Hwaseong. At SK hynix, the top DRAM experts are: CTO Dr. Cha Jin-se (concurrent with HBM), Head of DRAM R&D Dr. Park Myoung-soo (concurrent with HBM), Head of M16 Operations Dr. Lee Kang-hyun (concurrent with HBM), and Head of Cell Architecture Dr. Kim Dae-hyun. The SK hynix DRAM team is ~4,500 engineers across Cheongju and M16. At Micron, the top DRAM experts are: Head of Technology Dr. Scott DeBoer, Head of Hiroshima Operations [TBD], Head of Cell Architecture Dr. Steven Pradhan (concurrent with NAND), and Head of HBM Dr. Praveen Vaidyanathan. The Micron DRAM team is ~3,500 engineers across Hiroshima and the new New York fab.

The 2025-2027 DRAM capex is the cleanest single read on the AI capex cycle's memory leg. Combined DRAM-specific capex 2025-2027 across the 3 IDMs is $35B+ (Samsung $14-16B/yr, SK hynix $12-14B/yr, Micron $7-9B/yr). The capex is concentrated at the 1c/1d DRAM node ramp + the HBM3E/HBM4 expansion + the 1g DRAM R&D. The new fab projects include Samsung Pyeongtaek P5, SK hynix M15X Cheongju + M17 (rumored), and Micron's $100B New York fab (ramp 2027-2030). The combined DRAM + HBM capex is the cleanest single read on the AI capex stack.

The 2026-2028 DRAM read-through is concentrated in 4 trades. (1) SK hynix is the cleanest HBM + DRAM exposure with the cleanest 1c yield curve and the closest Nvidia relationship. (2) Micron is the cleanest US-listed DRAM exposure with the strongest balance sheet and the cleanest 1-gamma (1c equivalent) ramp. (3) Samsung Electronics is the incumbent memory leader with the largest capacity and the most advanced process; the 1c ramp is the binding test. (4) CXMT (China) is the only latent challenger; a clean 1a equivalent ramp would be a structural risk to the 3 IDMs, a slow ramp would be a continuation of the supply discipline. The 2026-2028 DRAM demand at ~25-30% CAGR is the binding reason.

The first tell is the 1c DRAM node yield ramp. The 1c node is the current leading edge, in mass production at Samsung Pyeongtaek P4 and SK hynix M16, and in mass production at Micron Hiroshima as 1-gamma. A clean 1c yield ramp at 80%+ is a re-rating catalyst; a yield stall at 60-70% is a multiple-compression event. Watch the quarterly yield disclosures as the cleanest read on the 1c ramp.

The second tell is the HBM4 customer allocation. The HBM4 supply for 2027 (Nvidia Rubin + AMD MI400) is being negotiated now. A clean allocation across all 3 IDMs is a re-rating catalyst; a SK hynix-dominant allocation is a multiple-compression event for Samsung and Micron. The third tell is the DDR5 ASP trajectory. The DDR5 ASP premium over DDR4 is ~30-40% per-bit; a maintained premium is a re-rating catalyst, a compressing premium is a multiple-compression event. The fourth tell is the LPDDR6 sampling. Samsung, SK hynix, and Micron are all sampling LPDDR6 in 2026-2027; a clean LPDDR6 qualification at Apple (iPhone 18) is a re-rating catalyst. The fifth tell is the CXMT 1a/1b equivalent ramp. CXMT is sampling 1a/1b equivalent DRAM; a clean volume ramp would be a structural risk to the 3 IDMs, a slow ramp would be a continuation of the supply discipline. The sixth tell is the new fab construction. Samsung Pyeongtaek P5, SK hynix M15X Cheongju, and Micron New York are all in construction/expansion in 2026-2027; clean construction milestones are re-rating catalysts, construction delays are multiple-compression events.