GPU / NPU / ASIC / TPU / CPU Deep Dive: How Nvidia, AMD, Broadcom, Alphabet, Apple, and Intel Are Reshaping the $400B AI Compute Market - Performance, Bottlenecks, Supply Chain, and Demand

The AI compute market in 2026 is a $400B+ market segmented into 5 binding architectures. The 5 architectures are: (1) GPU (the cleanest single parallel compute architecture, Nvidia H100/H200/B100/B200/GB300 + AMD MI300/MI325/MI350 + Intel Gaudi 3); (2) NPU (the cleanest single on-device AI accelerator, Apple Neural Engine + Qualcomm Hexagon + Intel NPU + MediaTek APU + Samsung Electronics NPU); (3) ASIC (the cleanest single custom AI accelerator, Broadcom custom ASIC for hyperscalers + Marvell custom silicon + Alchip ASIC); (4) TPU (the cleanest single Google custom AI accelerator, Alphabet TPU v5/v6/v7); (5) CPU (the cleanest single general-purpose compute, Intel Xeon + AMD EPYC + Apple M-series).

The 2025 AI compute market is structurally driven by the AI training + inference + on-device cycle. (1) AI training: the Nvidia H100/H200/B100/B200/GB300 + AMD MI300/MI325/MI350 + Broadcom custom ASIC + Alphabet TPU cycle drives the AI training market, with 2025 AI training revenue at ~$150B. (2) AI inference: the Nvidia H100/H200/L40S/T4 + AMD MI300/MI325 + Broadcom custom ASIC + Alphabet TPU + Intel Xeon + AMD EPYC cycle drives the AI inference market, with 2025 AI inference revenue at ~$200B. (3) On-device AI: the Apple Neural Engine + Qualcomm Hexagon + Intel NPU cycle drives the on-device AI market, with 2025 on-device AI revenue at ~$50B (mostly bundled with smartphone + PC + auto).

The 2025-2026 AI compute customer base is structurally concentrated in 5 legs. (1) The hyperscaler: Microsoft (the cleanest single OpenAI customer, ~$80B AI capex 2025), Alphabet (the cleanest single TPU + Gemini customer, ~$75B AI capex 2025), Amazon (the cleanest single Anthropic + Trainium customer, ~$100B AI capex 2025), Meta (the cleanest single Llama + custom ASIC customer, ~$60-100B AI capex 2025), Oracle (the cleanest single OCI + Nvidia customer, ~$15B AI capex 2025). (2) The neocloud: CoreWeave (the cleanest single Nvidia-only neocloud, ~$10B AI capex 2025), Lambda (the cleanest single AI neocloud, ~$3B AI capex 2025), xAI (the cleanest single Colossus supercomputer, ~$10B AI capex 2025), Anthropic (the cleanest single AI lab neocloud, ~$5B AI capex 2025), OpenAI (the cleanest single AI lab neocloud, ~$15B AI capex 2025). (3) The enterprise: Apple (the cleanest single on-device AI customer), Tesla (the cleanest single Dojo + FSD customer), Goldman Sachs (the cleanest single finance AI customer), JPMorgan (the cleanest single finance AI customer).

The GPU architecture is the dominant AI compute architecture in 2025, with Nvidia holding ~70% of the data center GPU market + AMD at ~12% + Intel Gaudi 3 at ~3% + others ~15%. The Nvidia GPU roadmap is: H100 (2023, 80GB HBM3, 700W TDP), H200 (2024, 141GB HBM3E, 700W TDP), B100 (2025, 192GB HBM3E, 700W TDP), B200 (2025, 192GB HBM3E, 1000W TDP), GB300 (2025-2026, 288GB HBM3E, 1200W TDP), Rubin (2026, HBM4, 1800W TDP), Rubin Ultra (2027-2028, HBM4E, 2300W TDP). The 2025-2026 Nvidia GPU revenue is ~$120-150B, projected to grow to $200-300B by 2028E.

The AMD GPU roadmap is: MI300 (2024, 192GB HBM3, 750W TDP), MI325 (2025, 256GB HBM3E, 1000W TDP), MI350 (2026, 288GB HBM3E, 1000W TDP), MI400 (2027-2028, HBM4, 1500W TDP). The 2025 AMD GPU revenue is ~$8-10B, projected to grow to $20-30B by 2028E. The Intel Gaudi 3 GPU roadmap is: Gaudi 3 (2024, 128GB HBM2E, 900W TDP), Gaudi 4 (2026, HBM3E, 1000W TDP). The 2025 Intel GPU revenue is ~$1-2B, projected to grow to $3-5B by 2028E. The Nvidia + AMD + Intel GPU + Broadcom + Marvell custom ASIC + Alphabet TPU + Apple M-series + Qualcomm Hexagon NPU + MediaTek APU supply chain is built on 5 binding layers: HBM, CoWoS, SiP, foundry, and the in-house chip design IP.

The HBM + CoWoS + SiP supply chain is the cleanest single constraint. HBM is dominated by SK hynix (52% share, HBM3E + HBM4), Samsung Electronics (20%, HBM3E), and Micron (28%, HBM3E + HBM4). The 2025 HBM market is ~$40B, projected to grow to $80-120B by 2028E. CoWoS is dominated by TSMC (75% share, CoWoS-S + CoWoS-L + SoIC). The 2025 CoWoS capacity is ~38K wpm, projected to grow to ~110K wpm by 2027-2028E. SiP (System-in-Package) is dominated by TSMC + Amkor + ASE Technology. The foundry layer is dominated by TSMC (~55% share), Samsung Electronics (~15%), and Intel (~15%). The 2025 AI compute capex is ~$1.5T cumulative (2025-2027), which is the cleanest single read on the AI capex cycle.

The NPU (Neural Processing Unit) is the cleanest single on-device AI accelerator, with Apple Neural Engine as the cleanest single NPU leader. The Apple Neural Engine is integrated into every M-series Mac + A-series iPhone + iPad + Apple Watch, with 38 TOPS in the M4 + A18 Pro (vs 17 TOPS in M1 + A14). The Qualcomm Hexagon NPU is the cleanest single Android NPU, with 45 TOPS in the Snapdragon 8 Gen 4 + Snapdragon X Elite 2. The MediaTek APU is the cleanest single mid-range Android NPU, with 25-30 TOPS in the Dimensity 9400. The Intel NPU is the cleanest single x86 NPU, with 13 TOPS in the Lunar Lake + Arrow Lake + Panther Lake. The on-device AI market in 2025 is ~$50B (mostly bundled with smartphone + PC + auto), and the on-device AI mix is projected to grow from ~5% in 2023 to ~20% in 2026E.

The ASIC (Application-Specific Integrated Circuit) is the cleanest single custom AI accelerator, with Broadcom as the cleanest single hyperscaler ASIC supplier. Broadcom custom ASIC customers include Alphabet TPU (the cleanest single AI ASIC + Ethernet combo, the binding partner for Alphabet TPU + Cloud networking), Meta MTIA (the cleanest single AI ASIC for Meta Llama training), Microsoft Maia (the cleanest single AI ASIC for Microsoft + OpenAI), Amazon Trainium 2/3 (the cleanest single AI ASIC for Amazon + Anthropic). Marvell custom silicon is the second cleanest single ASIC supplier, with Alchip as the third cleanest single ASIC supplier (the cleanest single Asia ASIC + AI accelerator). The 2025 ASIC market is ~$30B, projected to grow to $80-120B by 2028E at ~50% CAGR.

The TPU (Tensor Processing Unit) is the cleanest single Google custom AI accelerator, with Alphabet TPU v5/v6/v7 as the cleanest single TPU leader. The Alphabet TPU v6 (2025) is the cleanest single 400W TPU with 256GB HBM3E, used internally for Alphabet Search + Gemini + Waymo + Cloud Vertex AI. The Alphabet TPU v7 (2026) is the cleanest single 500W TPU with 512GB HBM4, projected for Alphabet Gemini 4 + Cloud Vertex AI. The TPU is the cleanest single vertically-integrated AI accelerator (designed + manufactured by Broadcom for Alphabet). The CPU (Central Processing Unit) is the cleanest single general-purpose compute, with Intel Xeon + AMD EPYC + Apple M-series as the cleanest single CPU leaders. The CPU is the cleanest single host for the AI accelerator (every Nvidia GPU server has 2x Intel Xeon or 2x AMD EPYC), and the CPU market in 2025 is ~$80B with Intel at ~$30B + AMD at ~$25B + Apple at ~$15B + others at ~$10B.

The 2026-2028 AI compute bottleneck is concentrated in 4 binding constraints. (1) HBM: the HBM3E + HBM4 supply is 100% allocated to Nvidia + AMD + Broadcom + Alphabet + Apple, and the HBM capacity is the cleanest single bottleneck for the AI compute cycle. (2) CoWoS: the TSMC CoWoS-S/L capacity is 100% allocated to Nvidia + AMD + Broadcom + Apple, and the CoWoS capacity is the cleanest single advanced packaging bottleneck. (3) Power: the AI data center power demand is 100+ kW/rack in 2026E, and the power + grid + substation capacity is the cleanest single data center bottleneck. (4) Liquid cooling: the AI accelerator TDP is 1200W+ in 2025 (vs 700W for H100), and the liquid cooling (DLC + immersion) is the cleanest single thermal bottleneck.

The 2026-2028 AI compute performance gap is the cleanest single read on the AI compute cycle. The 5 architectures have distinct performance characteristics: (1) Nvidia GPU leads in FP16 + FP8 + FP4 throughput, with the GB300 delivering ~1.5 ExaFLOPS FP8 per node (vs ~1 ExaFLOPS for B200) and the Rubin delivering ~3 ExaFLOPS FP4 per node. (2) AMD GPU is the cleanest single Nvidia alternative, with the MI350 delivering ~1.2 ExaFLOPS FP8 per node and the MI400 delivering ~2.5 ExaFLOPS FP4 per node. (3) Broadcom custom ASIC is the cleanest single hyperscaler-specific AI accelerator, with Alphabet TPU v6 delivering ~1 ExaFLOPS FP8 per chip and the v7 delivering ~2 ExaFLOPS FP4 per chip. (4) Apple Neural Engine is the cleanest single on-device AI accelerator, with 38 TOPS in the M4 + A18 Pro. (5) Intel Xeon + AMD EPYC is the cleanest single CPU host, with the Xeon 6 + EPYC Turin delivering ~200-500 GFLOPS FP16 per core.

The 2026-2028 AI compute demand is the cleanest single read on the AI capex cycle. The combined AI compute capex 2025-2027 is $1.5T+ (Nvidia + AMD + Broadcom + Alphabet + Apple + Intel + Qualcomm + Marvell + hyperscaler custom silicon). The capex is concentrated at the AI training + inference + on-device + custom ASIC cycle, and the 2027-2028 AI compute capex is the binding reason. The 2026-2028 AI compute market at ~25% CAGR is the cleanest single read on the AI capex cycle.

The AI compute expert pool is structurally concentrated in 6 hubs. At Nvidia Santa Clara: CEO Jensen Huang, CTO Michael Kagan, Head of GPU Architecture Dr. Jonah Alben, and Head of HBM Integration Dr. Brian Kelleher. The Nvidia AI compute team is ~10,000 engineers. At AMD Santa Clara: CEO Dr. Lisa Su, CTO Mark Papermaster, Head of GPU Architecture Dr. David Wang, and Head of MI300/MI400 Integration Dr. Andrew Diehl. The AMD AI compute team is ~5,000 engineers. At Broadcom Palo Alto: CEO Hock Tan, CTO Dr. Ed Redmond, Head of Custom ASIC Dr. Rajiv Ramaswami, and Head of Tomahawk Ultra Dr. Dan Dooley. The Broadcom AI compute team is ~3,000 engineers.

The 2026-2028 AI compute read-through is concentrated in 6 trades. (1) Nvidia is the cleanest single GPU pure-play with ~70% data center share + the cleanest single HBM + CoWoS + software (CUDA) moat. (2) AMD is the cleanest single GPU alternative with the cleanest single CPU + GPU integrated stack. (3) Broadcom is the cleanest single custom ASIC supplier with the cleanest single hyperscaler networking + ASIC combo. (4) Alphabet is the cleanest single TPU + integrated AI stack (Search + Workspace + Cloud + TPU). (5) Apple is the cleanest single on-device NPU + integrated consumer AI stack. (6) Intel is the cleanest single CPU + foundry + NPU integrated stack (Xeon + 18A + NPU). The 2026-2028 AI compute demand at ~25% CAGR is the cleanest single read on the AI capex cycle.

The first tell is the Nvidia GB300 + Rubin ramp. The GB300 NVL72 is the cleanest single AI server in 2025, and the Rubin NVL144 is the cleanest single AI server in 2026. A clean GB300 + Rubin ramp is a re-rating catalyst for Nvidia + the AI capex stack (SK hynix + TSMC + Coherent + Innolight); a GB300 + Rubin delay is a multiple-compression event.

The second tell is the AMD MI350 + MI400 customer wins. The MI350 is shipping in 2026, and the MI400 is sampling in 2026-2027. A clean Microsoft + Meta + Oracle + hyperscaler MI350 + MI400 customer win is a re-rating catalyst for AMD; a customer loss is a multiple-compression event. The third tell is the Broadcom custom ASIC customer mix. The Alphabet + Meta + Microsoft + Amazon custom ASIC customer mix is the cleanest single demand driver. A clean customer mix gain is a re-rating catalyst for Broadcom; a customer loss is a multiple-compression event. The fourth tell is the Alphabet TPU v7 launch. TPU v7 is the cleanest single 500W TPU with 512GB HBM4, projected for Alphabet Gemini 4 + Cloud Vertex AI in 2026. A clean TPU v7 launch is a re-rating catalyst for Alphabet; a delayed launch is a multiple-compression event. The fifth tell is the Apple Neural Engine 5th-gen. The Apple Neural Engine 5th-gen is the cleanest single on-device AI accelerator for iPhone 17/18 + M5 Mac, projected at 50+ TOPS. A clean Neural Engine 5th-gen launch is a re-rating catalyst for Apple; a delayed launch is a multiple-compression event. The sixth tell is the Intel 18A + Xeon 6 + NPU ramp. The 18A foundry + Xeon 6 + NPU ramp is the cleanest single test of the Intel Foundry + Intel AI thesis. A clean 18A + Xeon 6 + NPU ramp is a re-rating catalyst for Intel; a foundry yield issue is a multiple-compression event.