Advanced Packaging Deep Dive: How TSMC CoWoS, Samsung I-Cube, Intel EMIB, and Amkor Built the Single Most Binding Constraint of the AI Accelerator Cycle

Advanced packaging is the single most binding constraint of the AI accelerator cycle, and the supply is structurally concentrated. The 5 leading-edge suppliers are: TSMC (~75% share with CoWoS), Samsung Electronics (~10% with I-Cube), Intel (~10% with EMIB + Foveros), and the OSATs (Amkor, ASE Technology, JCET) at ~5% combined. The 2026 advanced packaging market is ~$50B, projected to grow to $90-100B by 2028E at ~25% CAGR driven by AI accelerator demand. The customer base is structurally concentrated in 4 names: Nvidia (H100/H200/B100/B200/GB300 + Rubin), AMD (MI300/MI325/MI350), Broadcom (custom ASICs), and Apple (M-series + A-series + Neural Engine). The top-4 customers are ~85% of advanced packaging demand.

The advanced packaging taxonomy is built on 2 binding axes: 2.5D vs 3D, and interposer type. 2.5D packaging places multiple chiplets side-by-side on a silicon interposer or RDL (redistribution layer) interposer, with the interposer hosting the high-density routing between chiplets. 3D packaging stacks chiplets vertically with through-silicon-vias (TSVs) or hybrid bonding (Cu-Cu direct bonding at the wafer level), enabling the highest density and the shortest interconnect length. The 5 leading-edge architectures are: (1) TSMC CoWoS-S (silicon interposer, the original 2.5D architecture, used for H100/H200); (2) TSMC CoWoS-L (local silicon interconnect + RDL interposer, used for B100/B200/GB300); (3) TSMC CoWoS-R (RDL only, no silicon, used for cost-sensitive parts); (4) Samsung I-Cube (silicon interposer, competitive with CoWoS-S); (5) Intel EMIB (embedded multi-die interconnect bridge, the cleanest 2.5D alternative) + Foveros (3D face-to-face hybrid bonding).

The 2025-2026 advanced packaging supply-demand is structurally imbalanced. TSMC CoWoS capacity is ~38K wafers/month in 2025 and projected to ramp to ~75K wafers/month in 2026E (with the SoIC 3D packaging adding another ~10K wpm in 2026-2027E). The 2026 CoWoS capacity is ~100% allocated to the top-4 customers (Nvidia, AMD, Broadcom, Apple), and the 2027 capacity is being negotiated now. The structural supply discipline is the binding reason the advanced packaging market has held 2-3x above the historical packaging pricing curve, and the AI accelerator capex cycle is the binding demand driver. The 2026-2028 advanced packaging read-through is concentrated in the CoWoS expansion, the SoIC 3D ramp, and the substrate supply chain (Ibiden, Shinko Electric).

Advanced packaging technology is built on 5 binding layers. (1) The interposer: the silicon interposer (used in CoWoS-S, CoWoS-L, I-Cube) is a 100x100mm+ silicon substrate with through-silicon-vias (TSVs) and fine-pitch metal routing. The silicon interposer is manufactured on a 65nm/45nm/28nm logic process, which is the binding reason the CoWoS-S capacity is constrained by 12-inch wafer supply. The RDL interposer (used in CoWoS-R, CoWoS-L) is an organic-based routing layer with no silicon, which is cheaper but has lower routing density. The interposer technology is the binding moat for TSMC CoWoS and Samsung I-Cube. (2) The chiplet integration: the chiplets (the GPU/CPU/HBM/misc dies) are integrated onto the interposer using either flip-chip bumping (the legacy approach) or hybrid bonding (the leading-edge approach, used in 3D packaging). The chiplet integration is the binding moat for Intel Foveros and TSMC SoIC.

(3) The 3D hybrid bonding: hybrid bonding is Cu-Cu direct bonding at the wafer level, with a bonding pitch of <10 micron (vs 50-100 micron for flip-chip bumping). The 3D hybrid bonding enables the highest density and the shortest interconnect length, which is the binding reason for HBM stacking (HBM3E uses TSV-based 12-Hi stack, HBM4E uses hybrid bonding for 16-Hi). The 3D hybrid bonding is the cleanest single R&D moat for TSMC SoIC (System on Integrated Chip) and Intel Foveros. (4) The substrate: the advanced packaging substrate (the 100x100mm+ organic substrate that hosts the CoWoS/I-Cube/EMIB package) is dominated by Ibiden (~40% share), Shinko Electric (~30%), Samsung Electro-Mechanics (~15%), AT&S (~10%), and Unimicron (~5%). The substrate supply is the second binding constraint (after the interposer supply), and the substrate ASP is ~$200-500 per advanced package, vs $20-50 for a legacy package substrate.

(5) The test/burn-in: the advanced package test (including Known-Good-Die (KGD) test, final test, and burn-in) is dominated by the OSATs (Amkor, ASE Technology, JCET, Powertech Technology). The advanced package test ASP is ~$50-200 per package, which is a meaningful margin contributor for the OSATs. The 5 layers together are the binding advanced packaging technology stack, and the 5+ year R&D moat in each layer is the structural reason the 5 leading-edge suppliers control ~100% of the leading-edge market.

TSMC is the cleanest advanced packaging pure-play with ~75% revenue share, dominated by CoWoS. TSMC's advanced packaging capacity is concentrated at the Tainan fab (the original CoWoS site), the Hsinchu advanced packaging center (the CoWoS-L + SoIC site), and the new Arizona advanced packaging center (the US-domiciled CoWoS site, ramping 2027-2028E). TSMC's CoWoS capacity is ramping from ~38K wafers/month in 2025 to ~75K wafers/month in 2026E to ~110K wafers/month in 2027-2028E. The CoWoS-L mix is ~70% of 2026E capacity, CoWoS-S is ~25%, and CoWoS-R is ~5%. The SoIC 3D packaging (used for HBM4E stacking and 3D logic) is ramping from ~5K wafers/month in 2026E to ~25K wafers/month in 2028E. The TSMC advanced packaging capex is projected at $20-25B in 2025-2027, which is the cleanest single read on the AI capex cycle's packaging leg.

Samsung Electronics is the second-largest advanced packaging supplier with ~10% revenue share, dominated by I-Cube. Samsung's I-Cube architecture is competitive with TSMC CoWoS-S, and the I-Cube 2.0 (with local silicon interconnect, competitive with CoWoS-L) is sampling in 2026. Samsung's advanced packaging capacity is concentrated at Hwaseong (the original I-Cube site) and the new Cheonan advanced packaging center (the I-Cube 2.0 + 3D site, ramping 2027-2028E). Samsung's I-Cube capacity is ramping from ~3K wafers/month in 2025 to ~8K wafers/month in 2026E to ~15K wafers/month in 2028E. Samsung's I-Cube customers include Nvidia (some HBM3E base die), Broadcom (some custom ASICs), and the Samsung internal LSI division (Exynos + image sensors). Samsung's advanced packaging capex is projected at $3-5B in 2025-2027.

Intel is the third-largest advanced packaging supplier with ~10% revenue share, dominated by EMIB (2.5D) + Foveros (3D). Intel's EMIB architecture is the cleanest 2.5D alternative to CoWoS-S, and the Foveros architecture is the cleanest 3D hybrid bonding alternative to TSMC SoIC. Intel's advanced packaging capacity is concentrated at the Oregon D1X fab (the EMIB + Foveros site) and the new Arizona fab (the 18A + EMIB + Foveros site, ramping 2027-2028E). Intel's EMIB + Foveros customers include Intel internal (Meteor Lake + Arrow Lake + Lunar Lake + Panther Lake), Broadcom (some custom ASICs), and the Intel Foundry Services (IFS) external customers. The OSATs (Amkor, ASE Technology, JCET) are the test/burn-in + advanced substrate leg with ~5% combined share. Amkor is the cleanest US-listed advanced packaging OSAT with the new Arizona advanced packaging site (project announced 2024, ramping 2026-2027E).

The advanced packaging substrate (the 100x100mm+ organic substrate that hosts the CoWoS/I-Cube/EMIB package) is the second binding constraint after the interposer supply. The substrate supply is dominated by 5 vendors: Ibiden (~40% share, the cleanest leading-edge ABF substrate supplier), Shinko Electric (~30%, the second cleanest leading-edge supplier), Samsung Electro-Mechanics (~15%, the Samsung internal supplier), AT&S (~10%, the European substrate supplier), and Unimicron (~5%, the Taiwan substrate supplier). The advanced substrate ASP is ~$200-500 per advanced package, vs $20-50 for a legacy package substrate, and the advanced substrate supply is 100% allocated through 2026.

The customer base is structurally concentrated in 4 names: Nvidia (~55% of advanced packaging demand, for H100/H200/B100/B200/GB300 + Rubin), AMD (~18%, for MI300/MI325/MI350), Broadcom (~12%, for custom ASICs at Google, Meta, Microsoft, Amazon), and Apple (~5%, for M-series + A-series + Neural Engine). The top-4 customers are ~90% of advanced packaging demand, and the customer concentration is the structural reason the 2026-2028 advanced packaging capacity is 100% allocated.

The 2026-2028 advanced packaging demand is the cleanest single read on the AI capex cycle. The 2026 demand is ~$65-75B (up from ~$50B in 2025), the 2027 demand is ~$80-90B, and the 2028 demand is ~$90-100B. The demand growth is driven by: (1) the Nvidia Rubin ramp in 2026-2027 (each Rubin GPU needs ~1 CoWoS-L + 4-8 HBM4 + 1 base die); (2) the AMD MI400 ramp in 2027-2028 (similar CoWoS-L + HBM4 architecture); (3) the Broadcom custom ASIC ramp (each ASIC needs CoWoS-S or CoWoS-L); (4) the Apple M6/A20/Neural Engine ramp. The 2026-2028 advanced packaging demand at ~25% CAGR is the cleanest single read on the AI capex cycle's packaging leg.

The advanced packaging expert pool is structurally concentrated in 3 leading-edge IDMs + the top substrate suppliers. At TSMC, the top advanced packaging experts are: VP of R&D Dr. Y.J. Mii, Head of Advanced Packaging Dr. K.C. Hsu, Head of SoIC Dr. Shang-Yi Chiang (former), and Head of Tainan Advanced Packaging Dr. Marvin Liao. The TSMC advanced packaging team is ~3,500 engineers at Tainan + Hsinchu. At Samsung Electronics, the top advanced packaging experts are: Head of Foundry Dr. Han Seung-hoon, Head of I-Cube Dr. Kim Jae-hyun, and Head of Cheonan Packaging Dr. Park Sang-wook. The Samsung advanced packaging team is ~1,500 engineers at Hwaseong + Cheonan. At Intel, the top advanced packaging experts are: Head of Assembly/Test Dr. Babak Sabi (former), Head of EMIB Dr. Johanna Swan, and Head of Foveros Dr. Kim Hyo-jin. The Intel advanced packaging team is ~1,500 engineers at Oregon D1X + Arizona.

At the substrate suppliers, the top experts are: at Ibiden, Head of Substrate R&D Dr. Toshihiro Kishi; at Shinko Electric, Head of Substrate R&D Dr. Kenji Yamada. At the OSATs, the top experts are: at Amkor, CTO Dr. ChoonHeung Lee (former), Head of Advanced Packaging Dr. Yung-Han Chiu; at ASE Technology, CTO Dr. Tien Wu. The substrate + OSAT expert pool is ~3,000 engineers, and the geographic concentration is in Japan (Ibiden, Shinko) + Taiwan (ASE, Amkor Taiwan) + US (Amkor Arizona) + Korea (Samsung Electro-Mechanics) + China (JCET).

The 2026-2028 advanced packaging read-through is concentrated in 5 trades. (1) TSMC is the cleanest advanced packaging pure-play with ~75% share; the CoWoS-L + SoIC ramp is the cleanest single re-rating catalyst. (2) Samsung Electronics is the second advanced packaging supplier with I-Cube 2.0; the qualification at Nvidia + Broadcom is the binding test. (3) Intel is the third advanced packaging supplier with EMIB + Foveros; the IFS external customer wins are the binding test. (4) Ibiden and Shinko Electric are the cleanest advanced substrate exposures; the CoWoS-L + EMIB ramp is the binding demand driver. (5) Amkor and ASE Technology are the cleanest advanced packaging OSAT exposures; the Arizona + Taiwan advanced packaging capex is the binding growth driver. The 2026-2028 advanced packaging demand at ~25% CAGR is the cleanest single read on the AI capex cycle's packaging leg.

The first tell is the TSMC CoWoS-L capacity ramp. CoWoS-L is ~70% of the 2026 CoWoS mix, and a clean ramp from ~38K wpm 2025 to ~75K wpm 2026E to ~110K wpm 2027-2028E is a re-rating catalyst. Watch the quarterly CoWoS capacity disclosure as the cleanest single read on the AI capex cycle's packaging leg.

The second tell is the TSMC SoIC 3D sampling. SoIC 3D is the next-generation 3D hybrid bonding architecture, used for HBM4E stacking (16-Hi) and 3D logic. A clean SoIC sampling in 2026-2027 is a re-rating catalyst for TSMC; a slow SoIC ramp is a multiple-compression event. The third tell is the Samsung Electronics I-Cube 2.0 qualification. I-Cube 2.0 (with local silicon interconnect, competitive with CoWoS-L) is sampling in 2026; a clean qualification at Nvidia or Broadcom is a re-rating catalyst for Samsung, a qualification failure is a multiple-compression event. The fourth tell is the Intel Foveros IFS wins. Foveros is the cleanest 3D hybrid bonding alternative to TSMC SoIC; IFS external customer wins (e.g., Broadcom, Microsoft Maia, Amazon Trainium) are the binding test for the Intel Foundry thesis. The fifth tell is the Ibiden + Shinko Electric substrate capex. The advanced substrate is the second binding constraint after the interposer; a clean capex ramp at Ibiden + Shinko is a re-rating catalyst for the substrate cohort. The sixth tell is the Nvidia Rubin + AMD MI400 customer allocation. The Rubin + MI400 2027 CoWoS-L allocation is being negotiated now; a clean allocation across TSMC + Samsung is a re-rating catalyst, a TSMC-dominant allocation is a multiple-compression event for Samsung.