Sub-system
A data-centre switch is a box around a chip. Bandwidth, port count, buffering and congestion behaviour are decided by that single ASIC, and almost every switch in an AI cluster is built around silicon from a very small number of designers.
In one sentence
Merchant switch silicon is a packet-switching ASIC sold to system builders, integrating many high-speed ports, a switching fabric, packet buffers and the congestion-control logic that determines behaviour under load.
Two numbers characterise a generation: total switching capacity and radix, the number of ports at a given speed. Radix matters more than it sounds for AI, because a higher-radix chip connects the same number of nodes in fewer tiers — and every tier removed is a set of optical links removed, which is a direct saving in cost and power.
What separates one chip from another for this workload is not headline bandwidth but behaviour when the network is congested by an all-to-all exchange. Buffer architecture, congestion signalling and how finely traffic can be spread across equal-cost paths decide whether collectives complete predictably or leave accelerators waiting.
Switch vendors once designed their own ASICs. Developing a leading-edge switch chip became expensive enough that only very high volumes justify it, so most vendors now build systems around bought silicon and differentiate on software, optics integration and support. That is why so many competing switches contain the same chip.
Deep buffers absorb bursts and add latency and cost; shallow buffers keep latency low and require congestion control to work well. AI back-end fabrics generally favour the second with strong flow control, because a synchronised collective is hurt more by unpredictable delay than by a dropped burst.
Port count, speed and power of a switch follow from its ASIC, so a system builder's roadmap tracks the silicon roadmap. When a new generation doubles capacity, the whole industry's products move within a year — which is why network refresh cycles are as synchronised as they are.
2 of these are marked as a chokepoint: a handful of qualified suppliers, a multi-year lead time, or a single geography.
High-radix switch chips are large dies on advanced nodes, competing for the same wafers as accelerators.
Foundry vs IDMEvery port is a SerDes lane; the per-lane rate the chip supports sets what the whole system can do.
SerDes and retimersLarge switch dies with very high input-output counts increasingly need 2.5D packaging of their own.
Advanced packagingMerchant silicon exists because ports, rates and electrical interfaces are agreed in common, so a chip from one vendor drives optics from another. Without that every switch would be a closed system.
A high-radix switch die needs a substrate large enough to fan out hundreds of high-speed lanes without distorting them. Substrate size and layer count, not the die, is often what limits the package.
Package substratesOther pages in this map that name Switch silicon as something they cannot do without.
What each company supplies at this step, and — where a public figure exists — its share of this specific market — with what that share measures, the period it covers and who published it. Some rows also show the company’s own reported revenue for the segment covering this step, which is a different thing: it says how much this business matters to that company, not how much of the market it holds. Not a ranking and not a recommendation.
Supplies the merchant switch silicon most data-centre switches are built around.
Supplies switching and data-path silicon for network systems.
Designs switch silicon for both its specialised interconnect and its Ethernet platform.
Designs its own switching silicon and builds systems for AI data centres.
Designs its own switch silicon in-house, which is what lets Chinese clusters be wired without merchant parts.
Builds its own routing and switching silicon for the wide-area links that join data centres to each other.
Sells switch silicon for the PCIe and coherent links inside the rack — the layer beneath the Ethernet fabric.
Supplies the PCIe and Ethernet switches on the host-side and management networks around the fabric.
Designs its own routing silicon through Juniper, the third in-house stack alongside Cisco's and Broadcom's.
Designs its own switching chips, one of two Chinese vendors able to build a fabric without merchant parts.
Sells high-radix switch silicon as an independent alternative to the merchant incumbents.
Builds its own switch silicon for a fabric designed around collective operations rather than general traffic.
Whether radix growth keeps reducing the number of network tiers and therefore optics per node.
Whether co-packaged optics move the optical interface onto the switch package itself.
Whether any vendor returns to in-house silicon at the leading edge.
Each page explains one technology in plain language, states what it depends on, and names companies by what they supply at that step. Company roles are described qualitatively and deliberately carry no market shares, revenue figures or rankings — those change faster than an explainer can, and a stale number is worse than none. Ticker links point at company pages on this site and are provided for reference only.
Nothing here is investment advice, a recommendation, or a forecast. A company named on a page about a technology is not thereby a good investment, and the chokepoints described are structural facts about supply chains rather than predictions about prices. Technology moves; where a page describes something as unresolved or in development, that was true when it was written.