Sub-system
Every high-speed link in an AI system begins and ends in a SerDes — the circuit that turns parallel data into a serial stream and recovers it at the far end. It is among the hardest analogue design in the industry, and once a signal has travelled far enough, a separate chip is needed to reconstruct it.
In one sentence
A SerDes serialises parallel data onto a high-speed lane and recovers it at the receiver; a retimer is a chip that receives a degraded signal, reconstructs the data and re-transmits it cleanly, extending the reach of an electrical link.
Per-lane rates have doubled repeatedly, and each doubling makes the electrical channel worse: loss rises with frequency, reflections matter more, and crosstalk between neighbouring lanes grows. The receiver compensates with equalisation that models the channel and undoes its distortion, which is why a modern SerDes contains substantial digital signal processing rather than only analogue circuitry.
Past a certain reach the signal cannot be recovered, and the choice is to insert a retimer or convert to optics. A retimer is far cheaper and lower power than an optical link, so a great deal of system design is about arranging the physical layout so that retimed copper reaches where it needs to and optics are needed only beyond that.
A redriver amplifies what it receives, including the noise. A retimer recovers the clock, decides what the bits actually were, and transmits a clean signal — resetting the channel budget rather than boosting it. At current rates only retiming works over any useful distance, which is why a category of small chips became a real business.
Very few teams design their own SerDes at leading rates. It is licensed as hardened intellectual property from a small group of vendors, which is why the same physical-layer designs appear inside chips from companies that compete with each other, and why SerDes IP is a genuine dependency of any custom accelerator programme.
On the accelerator baseboard between the processor and the connector, inside active copper cables, on retimer cards in a chassis, and increasingly in memory and peripheral interconnect paths. They are individually inexpensive, present in large numbers, and their absence stops a system shipping.
1 of these is marked as a chokepoint: a handful of qualified suppliers, a multi-year lead time, or a single geography.
Modern SerDes needs advanced nodes for the digital equalisation that makes the analogue channel workable.
Foundry vs IDMRates, signalling and channel budgets are set by industry specifications; a chip that meets them interoperates and one that does not is unusable.
Very few teams design a leading-rate SerDes themselves; it is licensed as a hardened block from a short list of vendors. A design without access to one at the current rate simply cannot build the interface.
Semiconductor IPThe link is designed against a simulated channel long before silicon exists. If the model of the connector and cable is wrong, the error shows up as an unfixable bit-error rate in production.
EDA toolsOther pages in this map that name SerDes and retimers as something they cannot do without.
What each company supplies at this step, and — where a public figure exists — its share of this specific market — with what that share measures, the period it covers and who published it. Some rows also show the company’s own reported revenue for the segment covering this step, which is a different thing: it says how much this business matters to that company, not how much of the market it holds. Not a ranking and not a recommendation.
Supplies retimers and connectivity silicon for AI server and rack interconnect.
Supplies SerDes, retimers and active electrical cables.
Supplies SerDes intellectual property and interconnect silicon for custom designs.
Supplies SerDes IP and interconnect silicon used across switches and accelerators.
Licenses the high-speed interface IP that most accelerator and switch designs use rather than build.
Licenses competing interface IP and the verification environment that proves a link closes at speed.
Sells connectivity IP and custom silicon built around its own high-speed link designs.
Licenses interface and memory-link IP that shows up inside other vendors' controllers.
Supplies PCIe retimers and memory interface silicon, the listed Chinese entrant in a market of four vendors.
Supplies the redrivers and retimers on the interfaces that leave the board.
Supplies the drivers and amplifiers at the electrical end of a link, before it becomes light.
Supplies PCIe retimers and the timing parts these links are clocked from.
Whether per-lane rates keep doubling, and how much reach is left in copper at each step.
Whether retimer content per accelerator keeps rising with system complexity.
Whether SerDes IP licensing stays concentrated as custom silicon programmes multiply.
Each page explains one technology in plain language, states what it depends on, and names companies by what they supply at that step. Company roles are described qualitatively and deliberately carry no market shares, revenue figures or rankings — those change faster than an explainer can, and a stale number is worse than none. Ticker links point at company pages on this site and are provided for reference only.
Nothing here is investment advice, a recommendation, or a forecast. A company named on a page about a technology is not thereby a good investment, and the chokepoints described are structural facts about supply chains rather than predictions about prices. Technology moves; where a page describes something as unresolved or in development, that was true when it was written.