High-bandwidth memory (HBM): stacked DRAM beside the processor
HBM is the reason a modern accelerator can move several terabytes a second between memory and arithmetic units. It is also one of the tightest constraints in the entire AI supply chain, because making it requires stacking, drilling and bonding DRAM dies at yields that only a few manufacturers can hit.
In one sentence
High-bandwidth memory is DRAM built as a vertical stack of thinned dies connected by through-silicon vias, sitting beside the processor on a shared package and talking to it over an interface thousands of bits wide.
Conventional memory sits on the motherboard and talks to the processor over a narrow, very fast bus — a few tens of bits, clocked as high as the signal integrity allows. That approach has hit its limit: pushing the clock higher costs energy that scales badly and the physical distance to the module cannot be reduced much further.
HBM takes the opposite route. It makes the interface enormously wide instead of enormously fast, which is only physically possible because the memory sits within millimetres of the processor on the same package. The width, rather than the clock rate, is where the bandwidth comes from — and the short distance is where the energy saving comes from.
How it works
How a stack is built
Several DRAM dies are thinned to a fraction of their original thickness, drilled with vertical copper connections through the silicon, aligned and bonded into a stack, and mounted on a logic base die that handles the interface. The stack is then placed next to the processor on a silicon interposer that carries the thousands of wires between them.
Why the yield problem compounds
A stack is only good if every die in it is good and every bond is good. Defects multiply rather than add, so a modest per-die yield becomes a poor stack yield, and the whole stack — with the working dies in it — is scrapped. This is why capacity cannot be added quickly and why the number of qualified suppliers is small.
It is bought as part of the package
The accelerator vendor buys stacks, qualifies them, and has them assembled onto the interposer with its own die. From the buyer's point of view HBM is not a component that can be sourced separately or upgraded later — it is fused into the product, which is why memory allocation decisions constrain accelerator shipments directly.
What this depends on
4 of these are marked as a chokepoint: a handful of qualified suppliers, a multi-year lead time, or a single geography.
Standard
The JEDEC HBM specification
Stack height, interface width, signalling and thermal limits are set by an industry standard, which is what lets processors and memory from different vendors be co-packaged at all.
TechnologyChokepoint
Through-silicon vias and die bonding
The vertical connections and the bonding that stacks the dies are the hard part of the process and the source of the yield loss.
One HBM stack consumes far more silicon area than the equivalent capacity of ordinary memory, so building it takes wafers away from the rest of the memory market.
Stacks are built on thermocompression or hybrid bonders that place thinned dies to sub-micron accuracy. The tools come from a handful of makers and their delivery times gate how fast stack capacity can be added.
Because a defect anywhere scraps the whole stack, each die has to be proved good before it is bonded. Test capacity and probe hardware are therefore part of the yield problem, not an afterthought.
What each company supplies at this step, and — where a public figure exists — its share of this specific market — with what that share measures, the period it covers and who published it. Some rows also show the company’s own reported revenue for the segment covering this step, which is a different thing: it says how much this business matters to that company, not how much of the market it holds. Not a ranking and not a recommendation.
Supplies the substrates the stacks are built on: a narrow Korean supply base sitting under an already scarce part.
What would change the picture
Whether stack yields improve enough to loosen supply, or whether each new generation resets the yield problem.
Whether the base logic die becomes customisable per customer, which would change who captures the value in a stack.
Whether a fourth qualified supplier appears, since three is unusually few for a component this critical.
Questions people ask about this
Why not just use more ordinary DRAM?
Bandwidth per package. Ordinary memory modules are limited by how many wires can reach them across a motherboard and how fast those wires can be clocked. HBM's interface is orders of magnitude wider because it only has to cross a few millimetres of interposer, and that width is exactly what a bandwidth-bound workload needs.
Why is HBM so often described as the bottleneck?
Because it fails three ways at once: only a handful of manufacturers can produce it, each stack consumes a large amount of wafer area, and the packaging step that attaches it is itself constrained. An accelerator cannot ship without it, so whichever of the three is tightest sets the ceiling on shipments.
Each page explains one technology in plain language, states what it depends on, and names companies by what they supply at that step. Company roles are described qualitatively and deliberately carry no market shares, revenue figures or rankings — those change faster than an explainer can, and a stale number is worse than none. Ticker links point at company pages on this site and are provided for reference only.
Nothing here is investment advice, a recommendation, or a forecast. A company named on a page about a technology is not thereby a good investment, and the chokepoints described are structural facts about supply chains rather than predictions about prices. Technology moves; where a page describes something as unresolved or in development, that was true when it was written.