Sub-system
Hybrid bonding joins two dies by pressing their polished faces together so that copper pads fuse directly and the surrounding dielectric bonds at the same time. Removing the solder bumps removes the thing that limited how closely connections could be packed — by more than an order of magnitude.
In one sentence
Hybrid bonding is a die- or wafer-joining technique in which copper pads and the surrounding dielectric on two polished surfaces bond directly to each other, with no solder, enabling interconnect pitches of a few microns or less.
Conventional stacking connects dies with tiny solder bumps. The bump has a minimum size and a minimum spacing, which sets a floor on how many connections fit in a given area and adds electrical parasitics and height. Hybrid bonding eliminates it: the connection is metal fused to metal.
The consequence is a step change in connection density, which makes genuine three-dimensional integration practical — logic stacked on logic, memory stacked directly on a processor — rather than merely placing dies side by side. It is also the direction memory stacking is heading as stack heights increase.
The surfaces must be flat to within a few nanometres and completely free of particles across the whole area, because there is no solder to absorb irregularity. That places extreme demands on chemical-mechanical polishing and on cleanliness. The bond is formed at room temperature and then annealed so the copper expands slightly and fuses across the interface.
Bonding whole wafers together is simpler but requires the two wafers to have identical die sizes and wastes any pairing where one die is bad. Bonding individual known-good dies onto a wafer avoids that waste and allows different die sizes, but is far slower per connection — which is why throughput of die-to-wafer bonders is a live constraint.
Stacking active dies puts one heat source directly beneath another, and the upper die insulates the lower one. Thermal design therefore constrains what can be stacked on what — which is why the first widespread uses stack memory or cache on logic rather than two high-power logic dies.
1 of these is marked as a chokepoint: a handful of qualified suppliers, a multi-year lead time, or a single geography.
Surface flatness at the nanometre scale across a full wafer is the prerequisite; without it the bond simply does not form reliably.
CMPThe bonders are made by a very small number of manufacturers and their throughput is a direct constraint on adoption.
Bonding equipmentBonding die to wafer is only worth its slower throughput if each die has been proven working first; otherwise the waste it was adopted to avoid comes straight back.
Metrology and testA single particle across the bonded area leaves a void, and there is no solder to absorb it. The cleans that follow planarisation are what decide whether the bond forms.
Resists and chemicalsOther pages in this map that name Hybrid bonding as something they cannot do without.
What each company supplies at this step, and — where a public figure exists — its share of this specific market — with what that share measures, the period it covers and who published it. Some rows also show the company’s own reported revenue for the segment covering this step, which is a different thing: it says how much this business matters to that company, not how much of the market it holds. Not a ranking and not a recommendation.
Supplies hybrid bonding equipment.
Supplies process steps for hybrid bonding and partners on integrated bonding systems.
Offers hybrid-bonded 3D stacking as a production packaging option.
A memory manufacturer for whom bonding technology governs future stack heights.
Supplies the wafer-to-wafer bonders and the alignment metrology the process is impossible without.
Supplies bonding and surface-preparation systems for the same step at the wafer level.
Supplies die-to-wafer hybrid bonders, which is the variant memory stacks are moving to.
Shipped hybrid-bonded image sensors in volume years before logic did, and still runs the largest installed base.
Is moving its memory stacks onto hybrid bonding as the layer count passes what adhesive stacking supports.
Whether memory stacks move to hybrid bonding as stack heights increase.
Whether bonder throughput improves enough to make the technique economic for high-volume parts.
Whether logic-on-logic stacking becomes practical despite the thermal constraint.
Each page explains one technology in plain language, states what it depends on, and names companies by what they supply at that step. Company roles are described qualitatively and deliberately carry no market shares, revenue figures or rankings — those change faster than an explainer can, and a stale number is worse than none. Ticker links point at company pages on this site and are provided for reference only.
Nothing here is investment advice, a recommendation, or a forecast. A company named on a page about a technology is not thereby a good investment, and the chokepoints described are structural facts about supply chains rather than predictions about prices. Technology moves; where a page describes something as unresolved or in development, that was true when it was written.
Plutux no es un asesor de inversiones. Los datos de mercado y el análisis generado por IA son solo informativos y educativos, no asesoramiento de inversión. Aviso legal